Electrostatic discharges (ESDs) from human handling of a metal-oxide silicon (MOS) IC chip permanently damage the MOS chip. Often the thin-oxide layer that isolates the gate electrode from the substrate of a MOS field effect transistor is irreparably ruptured by a voltage spike applied across it. A voltage spike or ESD is often applied to the gate because the gate electrode is connected to an external terminal or input pin of the IC chip. The external terminals are formed on an input pad. To prevent such damage from excessive electrostatic discharges, a protective device is often connected between the input pad and the gates of the input stage of the integrated circuit.
Such ESD protection becomes even more important as new generation of MOS devices are made with thinner gate oxides using, for example, submicron CMOS technologies. The thin-oxide MOS devices are extremely susceptible to the ESD damage. Therefore, ESD protection has become one of the most important elements with respect to the reliability of submicron CMOS technologies.
In submicron CMOS technologies, a lightly doped drain (LDD) structure is used to overcome the hot carrier degradation, while silicide diffusion is used to reduce the sheet resistances in the drain and source of the CMOS devices.
As MOS devices are made with thinner oxide, using LDD structures and silicided diffusion, the ESD protection circuit has become more important with respect to the reliability of compact MOS IC chips made using sub-micron CMOS technologies. The importance of ESD protection circuits is discussed in many references such as:
(1) C, Duvvury, R. A. McPhee, D. A. Baglee, and R. N. Rountree, "ESD Protection Reliability in 1-.mu.m CMOS Technologies", 1986 IRPS Proc., pp. 199-205.
(2) S. Daniel and G. Krieger, "Process and Design Optimization for advanced CMOS I/O ESD Protection Devices", 1990 EOS/ESD Symp. Proc., EOS-12, pp. 206-213.
(3) Y. Wei, Y. Loh, C Wang, and C. Hu, "MOSFET Drain Engineering for ESD Performance", 1992 EOS/ESD Symp. Proc., EOS-14 pp. 143-148.
ESD protection circuits are used to protect the sensitive thin-oxide gates of the MOS transistors by shunting ESD currents and pulling up (to VDD) or pulling down (to VSS or ground) the undesired voltage spikes (overshoots or undershoots) around the sensitive gates of the input stage. This current shunting and voltage clamping must be accomplished without affecting the normal signal paths, the operation of the transistors or the arrangement of the external terminals or pins of the IC chips. Normally the MOS IC chips operate using two voltage levels, namely, VSS and VDD. Each voltage level is applied to the IC through a common bus or node connected to a power pin of the IC chip. Generally, the ESD pulses have positive and negative polarities applied to both the VDD and the VSS nodes.
Conventional ESD protection circuits are disclosed in X. Guggenmos and R. Holzner, "A New ESD Protection Concept for VLSI CMOS Circuits avoiding Circuit Stress", 1991 EOS/ESD Symp. Proc., EOS-13 pp. 74-82, and in U.S. Pat. Nos. 4,692,781, 4,605,980, 4,745,450, 4,807,080, 4,819,046 and 5,001,529.
FIG. 1 shows one conventional ESD protection circuit 100 located between the input pad 105 and the CMOS input stage 110 which is to be protected against excessive high voltages.
Illustratively, the input stage 110 includes a thin-oxide PMOS device P1 and a thin-oxide NMOS device N1. The source 115 of the PMOS device P1 is connected to a VDD bus and its drain 125 is connected to the drain 130 of the NMOS device N1. The source 135 of the NMOS device N1 is connected to a VSS bus which is normally grounded. The gates 145, 150 of the PMOS and NMOS devices P1, N1 are connected together to form an input of the input stage 110. This input is connected to a terminal 155 of the ESD protection circuits 100. The terminal 155 is also the input terminal of the input stage 110. The output of the input stage 110 is formed by the common drain connection 160. Depending on the signal applied to the input of the input stage 115 at terminal 155, the output 160 of the input stage 110 is pulled up to VDD or pulled down to VSS.
The ESD protection circuit 100 is on the same IC chip containing the input pad 105 and the input stage 110. The ESD protection circuit 100 comprises a resistor R and two n-type MOS devices; a thin-oxide NMOS N2 and a thick-oxide NMOS N3.
The resistor R is connected in series between the terminal 170 of the input pad 105 and the terminal 155. This resistor may be a diffusion resistor which is formed by diffusion into the substrate of the integrated circuit in accordance with well known techniques. The thick-oxide NMOS device N3 has its drain 184 and its gate 186 connected to the terminal 170 of the input pad 105. The source 188 of the device N3 is connected to the VSS bus. The thin-oxide NMOS device N2 has its drain connected to the terminal 155 and its gate 192 connected to its source 194 and to the VSS bus.
The thin-oxide NMOS device N2 together with the diffused resistor R act as an isolation stage between the terminal 170 of the input pad 105 and the input stage 110. The thick-oxide NMOS N3 pulls down the voltage of terminal 170 to ground, i.e. to the grounded VSS. Thus, this ESD protection circuit 100 provides an ESD discharging path between the input pad 105 and ground. However, this ESD protection circuit 100 has no direct ESD discharging path to the VDD bus.
With no such direct ESD discharging path from the input pad 105 to the VDD bus, unexpected ESD damage occurs in the internal circuits of the IC chip as described in the following three references:
(1) C. Duvvury, R. N. Rountree, and O. Adams, "internal chip ESD phenomena beyond the protection circuit", IEEE Trans. on Electron Devices, vol. 35, no. 12, pp. 2133-2139, Dec., 1988,
(2) H. Terletzki, W. Nikutta, and W. Reczek, "Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress", IEEE Trans. on Electron Devices, vol. 40, no. 11, pp. 2081-2083, Nov., 1993, and
(3) C. Johnson, T. J. Maloney, and S. Qawami, "Two unusual HBM ESD failure mechanisms on a mature CMOS process", 1993 EOS/ESD Symp. Proc., EOS-15, PP. 225-231.
FIG. 2 shows another commonly used ESD protection circuit 200 connected between the input pad 105 and the input stage 110. As in the ESD protection circuit 100 of FIG. 1, one end of a resistor R is connected to the terminal 170 of the input pad 105. The resistor R may be a diffusion resistor or a polysilicon resistor (i.e., a resistor formed from polysilicon). The other end of the resistor R is connected to the terminal 155 which is connected to the gates 145, 150 of the MOS devices P1, N1 of the input stage 110.
The ESD protection circuit 200 provides two discharge paths; one from the terminal 155 to VSS through a diode D1 and another discharge path from the terminal 155 to VDD through a diode D2.
The first diode D1 has its anode 215 connected to the VSS bus and its cathode 220 connected to the terminal 155. The second diode D2 has its anode 255 also connected to the terminal 155, while its cathode 240 is connected to the VDD bus. While the circuit 200 provides some ESD protection, including two discharge paths, nevertheless ESD damage to the PMOS device P1 occurs in certain conditions. For example, when the VDD bus is floating, a positive 400 volt HBM (human body mode) ESD pulse with respect to the VSS bus, occurring at the input pad 105, damages the PMOS device P1.
FIG. 3 shows another ESD protection circuit 300 connected between the input pad 105 and the input stage 110. In this ESD protection circuit 300, the resistor R of FIG. 2 is dispensed with, so that the input pad 105 is directly connected to the input stage 110. In addition, the diodes D1, D2 of FIG. 2 are replaced with lateral npn bipolar junction transistors (BJT). The ESD protection circuit 300, has one npn BJT Q1 placed between the input pad 105 and the VSS bus and two npn BJTs Q2, Q3 placed between the input pad 105 and the VDD bus. The collectors 310, 315 of Q1 and Q2 and emitter 320 of Q3 are connected to the terminal 170. The emitter 325 of Q1 is connected to the grounded VSS. The emitter 330 of Q2 and collector 335 of Q3 are connected to VDD.
As with the ESD protection circuit 200 of FIG. 2, the ESD protection circuit 300 also provides two ESD discharge paths; between the input pad 105 and both the VSS and VDD buses.
Thus, the diodes D1, D2 of FIG. 2 and the BJTs Q1, Q2 and Q3 of FIG. 3 protect the input stage 110 from both positive and negative ESD voltages either between the input pad 105 and the VDD bus or between the input pad 105 and the VSS bus. As mentioned above, the ESD protection circuits 200 of FIG. 2 and 300 of FIG. 3 provide two ESD paths; one ESD path from the input pad 105 to the VDD bus, and a second ESD path from the input pad 105 to the VSS bus. However, despite these two discharge paths, the initial turn on voltage of the diodes D1, D2 of FIG. 2, or the BJTs Q1, Q2 and Q3 are usually higher than the breakdown voltage of the thinner gate oxides MOS devices P1, N1 of the input stage 110 in deep submicron CMOS technology.
FIG. 4 shows yet another commonly used ESD protection circuit 400 having the thin-oxide NMOS device N2 (also shown in FIG. 1) connected between the terminal 170 of the input pad 105 and the VSS bus which is grounded. As in FIG. 1, the resistor R is connected between the terminal 170 and the terminal 155 which is connected to the gates 145, 150 of the MOS devices P1 and N1 of the input stage 110. Similar to FIG. 2, the resistor R is a polysilicon resistor.
A thin-oxide PMOS device P2 is connected between the terminal 170 of the input pad 105 and the VDD bus. The drain 420 of the thin-oxide PMOS device P2 is connected to the terminal 170 of the input pad 105. The gate 430 and the source 440 of PMOS device P2 are connected to the VDD bus. Thus, the gates 192, 430 of each device N2, P2 are shorted to their respective sources 194 and 440, while the drains 190, 420 are connected to the terminal 170 of the input pad 105.
As in the ESD protection circuit 200 of FIG. 2 and 300 of FIG. 3, the ESD protection circuit 400 also provides two discharge paths (one path from the input pad 105 to the VDD bus, and a second path from the input pad 105 to the VSS bus). However, in ESD protection circuits using thin-oxide CMOS devices, the thin-oxide CMOS devices must be surrounded with double guard rings to overcome latchup which inhibits the CMOS devices. The thin-oxide NMOS N2 and PMOS P2 devices in the ESD protection circuit 400 are generally separated by the input pad 105. Therefore, the NMOS N2 and PMOS P2 are each surrounded by their own double guard rings. This results in even a larger total layout area.
Latchup occurs when the input signals are outside a predefined voltage range. When latchup occurs, a channel substrate diode, e.g., between a P-region of a PMOS and an N-substrate, becomes conducting and floods the substrate with charge carriers which could fire a parasitic thyristor, short circuiting the VDD and VSS supply voltages. A parasitic thyristor exists in both the ESD protection circuit 400 and the input stage 110. In FIG. 4, latchup may occur in the ESD protection circuit 400 or in the input stage 110.
FIG. 5 shows a circuit 500 having a parasitic thyristor formed by T1 and T2 between the input pad 105 and the VDD, VSS buses. This parasitic thyristor formed by T1, T2 is produced due to the p-n junctions of the two P2, N2 MOS devices of the ESD protection circuit 400 of FIG. 4. Normally, this parasitic thyristor is off and has no effect, as the reverse currents are drained off via resistors R1 and R2.
Similarly, in normal operation, a parasitic thyristor in the input stage 110 (FIG 4) is also inhibited and turned off. The parasitic thyristor in the input stage 110 is similar to the parasitic thyristor T1, T2 shown in FIG. 5, which is off during normal operation. However, if one of the protective devices (such as the diodes D1, D2 of FIG. 2, the BJTs Q1, Q2 or Q3 of FIG. 3 or MOS devices N2, N3, or P2 of FIGS. 1 and 4), acting as an additional emitter, is biased in the forward direction, then the thyristor in the input stage 110 may be turned on. This short circuits VDD to VSS and the resulting high current destroys the IC chip. To prevent this latchup effect, the input (or output) voltage must not exceed the VDD supply voltage or fall below VSS (i.e., ground potential). Alternatively, or in addition to, the current flowing through the devices of the ESD protection circuit should be limited.
It is the object of the present invention to provide an ESD protection circuit which provides a full protection for ICs of submicron CMOS technology. It is another the object of the present invention to provide ESD protection without latchup problems in the ESD protection circuit. It is yet another object of the present invention to reduce the layout area requirement needed for the ESD protection circuit thus reducing the size and cost of the IC chips and increasing packing density.
A further object of the present invention is to protect both the NMOS and PMOS devices of the input stage. Another object is to provide a voltage clamping effect on the input signals provided to the input stage to be protected. Yet another object is to provide such a protection without adversely affecting the normal operation of the input stage and internal circuits which are being protected, such as maintaining reliability and speed of operation of the internal circuits.